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Notas FreeRTOS

Notas que voy encontrando sobre el desarrollo de aplicaciones con FreeRTOS v9. La mayoria de las notas y ejercicios estan disponibles en los siguientes documentos (fuente: http://www.freertos.org/Documentation/RTOS_book.html ) mientras otras notas las encontré en el foro (fuente: http://www.freertos.org/FreeRTOS_Support_Forum_Archive/freertos_support_forum_archive_index.html ). Mastering the FreeRTOS Real Time Kernel A Hands On Tutorial Guide   FreeRTOS Reference Manual V9.0.0 Mutex Cuando se tiene dos tareas con la misma prioridad y utilizan el mismo mutex para acceder a un elemento, hay que hacer un taskYIELD() despues de entregar el mutex para forzar el cambio de una tarea a otra, de lo contrario solo se ejecuta una sola tarea. Fuente: freertos_mutex_never_giving 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 void vHello ( void * pvParameters){ ( void ) pvParameters; while ( 1 ) { if ( xSemaphoreTake(
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PSoC Creator Tools

List of executables under Creator/bin directory: cydsfit cydsfit -p <projfile> [-d <device>] [-s <srcpath>] [-f <flowtype>] [option ...] [--] [option ...]     -h                Display this help message.     -p <projfile>     Specify the name of the top level project file.     -d <device>       Override the selected device stored in the project file.     -s <srcpath>      Location of previously generated source. Used when merging                         user editable sections in to the new code. Defaults to                         using the current directory.     --                All arguments after the first double dash argument are used                         for Warp and the specific fitter driver exclusively. cypsocdebugger Usage: -t TRANSPORT [-pin CYD2STUB_PIPE -pout STUB2CYD_PIPE] [-e ENDIAN] [-p PORTSETTING1 [PORTSETTING2 ...]] [-jtag JTAGDEVICE [JTAGDEVICE ...]] cyprjmgr cyprjmgr.exe is a command line tool that
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Verilog modules

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PSoC Creator automatically generate a verilog file of your schematic design. This verilog file (PROJ_NAME.v) is under codegentemp directory located on your project directory. Here's the verilog from a empty project using the CY8CKIT-059 PSoC 5LP kit: // ====================================================================== // Design01.v generated from TopDesign.cysch // 01/11/2017 at 16:34 // This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! // ====================================================================== /* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */ `define CYDEV_CHIP_DIE_LEOPARD 1 `define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3 `define CYDEV_CHIP_REV_LEOPARD_ES3 3 `define CYDEV_CHIP_REV_LEOPARD_ES2 1 `define CYDEV_CHIP_REV_LEOPARD_ES1 0 `define CYDEV_CHIP_DIE_TMA4 2 `define CYDEV_CHIP_REV_TMA4_PRODUCTION 17 `define CYDEV_CHIP_REV_TMA4_ES 17 `define CYDEV_CHIP_REV_TMA
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